1. Field of the Invention
The present invention relates to charge pump circuits producing a voltage of a predetermined level through charge pumping operation of a capacitor, and more particularly, it relates to a charge pump circuit for producing a negative substrate bias voltage, or a positive boosted voltage in a MOS (insulated gate type) semiconductor memory device.
2. Description of the Background Art
In a MOS memory (a memory device having MOS transistors as components), a substrate bias generator is generally employed to apply a bias voltage of a predetermined level to a bulk. The term "bulk" is used to represent a substrate itself and a well region in generic. A negative bias voltage is applied to a P type bulk, while a positive bias voltage is applied to an N type bulk. Application of such a bias voltage to a bulk is carried out for the following purposes: (1) stabilization of a threshold voltage of a MOS transistor, (2) reduction of a junction capacitance between a bulk and a source/drain region to achieve a fast operation, and (3) suppression of production of a parasitic MOS transistor between a signal interconnection line and a substrate or a well region.
In a recent memory device such as DRAM (Dynamic Type Random Access memory), an on-chip bias generator is employed which is formed on a memory chip to internally generate a bias voltage in the memory device, in order to implement a memory device operable with a single power supply voltage.
Such a bias generator includes a charge pump circuit utilizing charge pumping operation of a capacitor as shown in FIG. 1.
Referring to FIG. 1, a conventional charge pump circuit includes a capacitor 3 responsive to a repetition signal (simply referred to as a clock signal hereinafter) .phi. for capacitively coupling the signal .phi. to a node N1, a diode-connected N channel MOS transistor 2 provided between node N1 and a node N2 supplying a ground potential (GND), another diode-connected N channel MOS transistor 1 provided between node N1 and a node N0 producing a negative bias voltage Vbb.
MOS transistor 1 has a drain and a gate connected together to node N0, and a source connected to node N1. MOS transistor 2 has a drain and a gate connected together to node N1, and a source connected to node N2. Bulks of MOS transistors 1 and 2 are connected to node N0, in order to reliably reverse-biasing PN junction between the bulk and the source/drain region of each of MOS transistors 1 and 2. Now, operation of charge pumping circuit shown in FIG. 1 will be described with reference to FIG. 2 which in turn is an operating waveform diagram of the charge pump circuit of FIG. 1.
A node N3 receives the clock signal .phi. which oscillates between a power supply potential Vcc and ground potential GND. When the signal .phi. goes high at the time t0, the potential at node N1 goes high through capacitive coupling of capacitor 3. Assuming that a coupling efficiency of capacitor 3 to node N1 is k, the potential at node N1 attains k.multidot.Vcc. In general, k is nearly equal to "1". Transistor 2 has a threshold voltage Vth2, and is turned on with the relation of k.multidot.Vcc&gt;Vth2, to discharge the node N1. When the potential at node N1 is discharged to the potential of Vth2, the transistor 2 is turned off. During this period, the transistor 1 is kept turned off because the potential at node N1 changes within a range of k.multidot.Vcc to Vth2 and the transistor 1 is reversely biased. In FIG. 2, the potential at node N1 is shown rising from a negative potential to a positive potential. The negative potential at N1 is applied by transistor 1, and FIG. 2 waveform shows a transient state.
Upon falling of clock signal .phi. at the time t1, the potential at node N1 goes down to the level of Vth2-k.multidot.Vcc through capacitive coupling of capacitor 3. Responsively, transistor 2 is turned off. If a potential Vbb at node NO is higher than the potential Vth2-k.multidot.Vcc, a forward biasing is applied between the bulk and the source of N channel MOS transistor 1, so that a parasitic diode in the transistor 1 is turned on. Consequently, a current flows from node NO into node N1, to raise the potential at node N1 and to decrease the potential Vbb at node NO.
At the time t2, the clock signal .phi. again goes high, to turn on the transistor 2 and to turn off the transistor 1. The potential at node N1 rises from a negative potential to a positive potential and then is discharged to Vth2.
At the time t3, the clock signal .phi. goes down to turn on the transistor 1 (parasitic PN diode) and to turn off the transistor 1, so that the potential Vbb is decreased.
By repeating this operation, the potential at node NO is finally decreased to the level of Vth2-k.multidot.Vcc+Vpn1, where Vpn1 represents a forward residual potential (or a forward voltage drop) at the parasitic PN diode formed by the bulk (P type region) and the source (N type region) of N channel MOS transistor 1.
In a charge pump circuit shown in FIG. 1, negative charges (electrons) are injected into a substrate through charge pump pumping of the capacitor 3 at each falling of clock signal .phi., to reduce the substrate potential. In general, driving ability or current supply ability of charge pump circuit is determined by the product of the frequency f and amplitude Vcc of clock signal .phi. and the capacitance C of the charge pumping capacitor 3, f.multidot.Vcc.multidot.C.
FIG. 3 shows a schematic cross sectional view of an N type MOS transistor. Referring to FIG. 3, MOS transistor is formed in a P type well 102 formed on the surface of a P type substrate 100. MOS transistor includes high impurity concentration N+ regions 104 and 106, and a gate 110 formed on a channel region 109 between N+ regions 104 and 106. Although not explicitly shown in FIG. 3, a thin gate insulation film is formed between gate 110 and channel region 109. N+ region 104 is connected to a source electrode S, N+ region 106 is connected to a drain electrode D, and gate 110 is connected to a gate electrode G.
A P+ region 108 formed on the surface of P type well 102 is used to apply a bias voltage to P type well 102. If the shown MOS transistor is employed as transistor 1 or 2, P+ region 108 receives the negative bias voltage Vbb.
MOS transistor having a gate and a drain connected together operates in a saturation region to serve as a diode providing a voltage drop of its threshold voltage thereacross.
The reason why the bulks of MOS transistors 1 and 2 are connected to node NO to receive the bias voltage Vbb is for stabilizing the threshold voltages of these transistors 1 and 2, and for prevention of forward biasing between the bulk (well region) and N+ regions 104 and 106 (source and drain) of MOS transistors 1 and 2.
If the bulk (well) of transistor 2 is connected to node N2 to receive ground potential GND, the bulk (P type well 102) is forwardly biased with reference to N+ region 106 (drain) when node N1 is at a negative voltage in response to fall of the clock signal .phi.. In this condition, a current flows from node N2 (ground potential GND) to charge the node N1, resulting in deterioration of charge pumping from node N0.
As for transistor 1, if the bulk is coupled to the source, a forward bias voltage is developed across the bulk and the drain when the node N1 potential rises, resulting in rising of the node N0 potential. Thus, the bulks of the transistors 1 and 2 are connected to node N0 to receive the bias voltage Vbb.
Now, consider a state where parasitic PN diode is turned on in the transistor 1, with reference to FIG. 4.
Referring to FIG. 4, N+ region 106 and P+ region 108 and gate 110 are connected to node N0 to receive the bias voltage, while N+ region 104 is connected to node N1. When the potential at node N1 is lower than the potential at node N0 by a value exceeding the threshold voltage Vthl (or forward residual voltage Vpn 1), MOS transistor 1 turns on. In this state, a current flows through channel region 109 from N+ region 106 into N+ region 104. A current also flows from P+ region 108 through P type well 102 into N+ region 104, which accompanies injection of minority carriers (electrons) into P type well 102. P type well is electrically connected to P type substrate 100, and therefore injected minority carriers, as shown in FIG. 4 as a symbol, e., (electrons) diffuse into P type substrate 100 to reach another element. If injected minority carriers reach dynamic type memory cell including an access transistor formed of N channel MOS transistor, such minority carriers are trapped in a memory cell capacitor to cause a soft error. Also, such injected minority carriers may cause a substrate current to fluctuate threshold voltage of MOS transistors formed on the substrate, resulting in degraded reliability of a device.
Diode connected MOS transistor 1 causes a voltage drop of the threshold voltage thereacross. The minimal voltage of the bias voltage Vbb is given by Vth2-k.multidot.Vcc+Vpn1. The potential swing at node N1 is k.multidot.Vcc, and therefore the charges pumping efficiency is reduced by the amount of Vth2+Vpn1.